1/9 october 2002 STGW50NB60M n-channel 50a - 600v - to-247 powermesh? igbt ( l ) pulse width limited by safe operating area n high input impedance (voltage driven) n low on-voltage drop (v cesat ) n low gate charge n high current capability description using the latest high voltage technology based on a patented strip layout, stmicroelectronics has de- signed an advanced family of igbts, the power- mesh ? igbts, with outstanding performances. the suffix "m" identifies a family optimized to achieve very low saturation on voltage for frequency applications <10 khz. applications n motor control n welding equipments absolute maximum ratings type v ces v ce(sat)( 25c) i c STGW50NB60M 600 v < 1.9 v 50 a symbol parameter value unit v ces collector-emitter voltage (v gs = 0) 600 v v ecr reverse battery protection 20 v v ge gate-emitter voltage 20 v i c collector current (continuous) at t c = 25c 100 a i c collector current (continuous) at t c = 100c 50 a i cm ( n ) collector current (pulsed) 400 a p tot total dissipation at t c = 25c 250 w derating factor 2 w/c t stg storage temperature C65 to 150 c t j max. operating junction temperature 150 c to-247 1 2 3 internal schematic diagram
STGW50NB60M 2/9 thermal data electrical characteristics (t case = 25 c unless otherwise specified) off on (1) dynamic switching on rthj-case thermal resistance junction-case max 0.5 c/w rthj-amb thermal resistance junction-ambient max 30 c/w rthc-h thermal resistance case-heatsink typ 0.1 c/w symbol parameter test conditions min. typ. max. unit v br(ces) collector-emitter breakdown voltage i c = 250 a, v ge = 0 600 v i ces collector cut-off (v ge = 0) v ce = max rating, t c = 25 c v ce = max rating, t c = 125 c 10 100 a a i ges gate-emitter leakage current (v ce = 0) v ge = 20 v , v ce = 0 100 na symbol parameter test conditions min. typ. max. unit v ge(th) gate threshold voltage v ce = v ge , i c = 250 a 345v v ce(sat) collector-emitter saturation voltage v ge = 15v, i c = 30 a @25c v ge = 15v, i c = 30 a @100c v ge = 15v, i c = 50 a @25c v ge = 15v, i c = 50 a @100c 1.3 1.2 1.5 1.35 1.9 v v v v symbol parameter test conditions min. typ. max. unit g fs forward transconductance v ce = 15 v , i c = 18 a 22 s c ies c oes c res input capacitance output capacitance reverse transfer capacitance v ce = 25 v, f = 1 mhz, v ge = 0 4500 400 70 pf pf pf q g q ge q gc total gate charge gate-emitter charge gate-collector charge v ce = 480 v, i c = 50 a, v ge = 15 v 231 28 97 nc nc nc i cl latching current v clamp = 480 v , tj = 125c r g = 10 w 300 a symbol parameter test conditions min. typ. max. unit t d(on) t r turn-on delay time rise time v cc = 480 v, i c = 50 a r g =10 w , v ge = 15 v 45 30 ns ns (di/dt) on eon turn-on current slope turn-on switching losses v cc = 480 v, i c = 50 a r g =10 w , v ge = 15 v tj = 125c 1600 800 a/s j
3/9 STGW50NB60M electrical characteristics (continued) switching off note: 1. pulsed: pulse duration = 300 s, duty cycle 1.5 %. 2. pulse width limited by max. junction temperature. (**)losses include also the tail (jedec standardization) symbol parameter test conditions min. typ. max. unit t c cross-over time v cc = 480 v, i c = 50 a 450 ns t r (v off ) off voltage rise time r ge = 10 w , v ge = 15 v 130 ns t d ( off ) delay time 410 ns t f fall time 300 ns e off (**) turn-off switching loss 4 j e ts total switching loss 410 j t c cross-over time v cc = 480 v, i c = 50 a 730 ns t r (v off ) off voltage rise time r ge = 10 w , v ge = 15 v 265 ns t d ( off ) delay time tj = 125 c 565 ns t f fall time 440 ns e off (**) turn-off switching loss 6.6 j e ts total switching loss 810 j
STGW50NB60M 4/9 output characteristics normalized gate threshold voltage vs temp. transconductance transfer characteristics switching off safe operating area thermal impedance
5/9 STGW50NB60M total switching losses vs temperature collector-emitter on voltage vs temperature total switching losses vs gate resistance normalized break-down voltage vs temp. capacitance variations gate-charge vs gate-emitter voltage
STGW50NB60M 6/9 collector-emitter on voltage vs current total switching losses vs ic
7/9 STGW50NB60M fig. 2: test circuit for inductive load switching fig. 1: gate charge test circuit
STGW50NB60M 8/9 dim. mm. inch min. typ max. min. typ. max. a 4.85 5.15 0.19 0.20 d 2.20 2.60 0.08 0.10 e 0.40 0.80 0.015 0.03 f 1 1.40 0.04 0.05 f1 3 0.11 f2 2 0.07 f3 2 2.40 0.07 0.09 f4 3 3.40 0.11 0.13 g 10.90 0.43 h 15.45 15.75 0.60 0.62 l 19.85 20.15 0.78 0.79 l1 3.70 4.30 0.14 0.17 l2 18.50 0.72 l3 14.20 14.80 0.56 0.58 l4 34.60 1.36 l5 5.50 0.21 m 2 3 0.07 0.11 v 5 o5o v2 60o 60o dia 3.55 3.65 0.14 0.143 to-247 mechanical data
9/9 STGW50NB60M information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no res ponsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result f rom its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specificati ons mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devi ces or systems without express written approval of stmicroelectronics. ? the st logo is a registered trademark of stmicroelectronics ? 2002 stmicroelectronics - printed in italy - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malt a - morocco singapore - spain - sweden - switzerland - united kingdom - united states. ? http://www.st.com
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